- Active clock regeneration
- Individual time-delay compensation for each of the eight outputs based
on a real digital multitap delay line, 256 microsteps over the sampling
cycle
- Configuration via 1220 COMMANDER
- Provides both word clock and SDIF-2 audio delay. Audio delay handles up
to 32-bit word lengths
- Status LEDs on both front and rear panel. Mount unit with BNC connectors
backwards (»rack-mounted«) or BNC connectors facing
to front (»à la patchfield«)
- A total of 44 status LEDs
- Measurement and display of sample rate
- Input thresholds adjustable from 0.1..8.5V
- Flexible input shield connection. BNC shell connected to chassis
(»protection«), a 0.1µF/50V cap
(»RF«), or floating with
a common-mode input impedance of ~5kohms
- ±12V input common-mode range (»cap«
or »floating«)
- 'H' level of up to 4.25V when terminated with 75ohms, adjustable in steps
of 50mV. Idle voltage is double, but may be arbitrarily limited
- Well-defined 'H' and 'L' source impedance of 75ohms
- Continuous individual load supervision of any of the eight output lines
by our patent-pending Line Impedance Supervision (»LIS«)
procedure. Besides mismatch caused by wrong or missing line termina- tion,
LIS detects dielectric losses of insulators unsuited for RF. Adjustable
LIS tolerance window
- For further information on LIS, please refer to our »Technical
Comment 3 (11/93)«
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